25-11-2017 00:54:55

Open Source VHDL Verification Methodology (OSVVM): Advanced Verification for VHDL

Open Source VHDL Verification Methodology (OSVVM) is a comprehensive, advanced VHDL verification methodology.
Arrangør: IDA Embedded
Medarrangør: IDA IT

Open Source VHDL Verification Methodology (OSVVM) is a comprehensive, advanced VHDL verification methodology.   Like System Verilog’s UVM, OSVVM is a library of free, open-source code (packages).   OSVVM uses this library to implement functional coverage, constrained random tests, and Intelligent Coverage random tests with a conciseness, simplicity and capability that rivals other verification languages. 

In 2015 OSVVM added comprehensive error and message reporting (January, 2015.01) and memory modeling (June, 2015.06).    With this expanded capability, this presentation takes a look at the big picture methodology progressing transactions to randomization to functional coverage to intelligent coverage to alerts (error reporting) and logs (message reporting) to memory modeling. 

Worried about keeping up with the latest trends in verification?  With Intelligent Coverage, OSVVM has a portable, VHDL-based, intelligent testbench solution built into the library.  While Accellera is still working on their Intelligent testbench based portable stimulus solution (in the Portable Stimulus Working Group -PSWG), for OSVVM it is already here. 

Going Further

The class, Advanced VHDL Testbenches and Verification, will be offered in Copenhagen on November 16 to 20.  For more details see: www.firsteda.com/news/1511-vhdl-part3/

Author BIO:

Jim Lewis has over 28 years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group, co-founder of the Open Source VHDL Verification Methodology (OSVVM), and expert VHDL trainer for SynthWorks Design Inc.

Arrangør: Morten Zilmer

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